DPC/Dave/1 Issue 5
Copyright © 1984 Intelligent Software LTD.
The DPC Sound Chip has 22 internal registers, 17 of which are writeonly. 16 of these registers are associated with the sound generation, four R/W registers are for memory management, and one R/W register is used for interrupt control. The last writeonly register is used for setting the overall system configuration. Internal decoding is provided for a further 3 I/O registers, read and write strobes being brought out for use with external latches and tristate buffers on the data bus. Reset clears all 22 internal registers.
The 3 tone generators produce a square wave with frequency programmable from 30Hz to 125KHz which can be modified in various ways:
The noise channel is normally a 17 bit PN counter clocked from 31KHz, generating a pseudo white noise. The input to this counter can be changed to clock of any of the 3 tone channels, and the PN counter can be reduced in length to 15,11 or 9 bits. This counter can also be exchanged for the 7bit PN counter. The resulting noise is then passed through highpass and lowpass filters and a ring modulator, each controlled by the output of a different tone channel.
The 3 tone generator outputs and the noise generator output are routed to 2 amplitude control circuits (left and right). Each amplitude control consists of four 6bit writeonly registers (one for each sound) which are multiplexed onto an external 6bit D/A resistor network. In it's own time slot each channel outputs the value in it's amplitude register if the tone is high, else zero.
Either or both of the sound output channels may be turned nto 6bit D/A outputs, when they will constantly output the valuesin tone channel 0 amplitude registers. This is controlled by 2 bits in the writeonly sound configuration register. Three further bits may be used to synchronise the tone generators by holding them at a preset count until sync bit goes low.
Memory management consists of four read/write registers which may be
output onto A14-A21 pins by selecting the required register
with A14', A15'. This provides 256 * 16K pages. These
outputs may be tristated with BREQ.
Four latched interrupts are provided, a 1Hz interrupt for time
clock applications, an interrupt switchable between 50Hz,
1KHz or the outputs of tone generators 0 or 1, and two external
negative edge triggered interrupts. Each interrupt latch has it's own
enable and reset controlled by an 8bit write-only register. An
attempt to read this register will return the state of the four interrupt
latches and two interrupt input pins, and also two flipflops
toggling off the timer interrupts. The setting of any interrupt latch
will bring IRQ low (open drain).
50Hz/1KHz/tone generator interrupt selection is made by 2
bits in the sound configuration register.
Select signals are generated for ROM, cartridge, video RAM and video I/O. A 1MHz clock output is also provided.
A Z80 is reset provided on RSTO, either on switchon by
an external RC network on CAP, or a low going signal on
RSTI. The latter generates a 1mS reset pulse
synchronised to the falling edge of M1 to prevent loss of
data stored in dynamic RAM. THE RSTO output requires an
external 74ALS04 inverter to drive the system reset line at
the correct speed an inversion.
A writeonly system configuration register is used to set the system for 16/64K onboard RAM, 8/12MHz input clock, and wait states. The wait state generator can be programmed to give no wait states, waits on opcode fetch only, or waits on all memory accesses. Note that no wait is ever generated for access to video RAM, as this would conflict with Z80 clock stretch.
R0 W #A0
b7-b0
R1 W #A1
b3-b0
b5,b4
b6
b7
R2 W #A2
R0 but for tone channel 1.
R3 W #A3
R1 but for tone channel 1, except:
R4 W #A4
R0 but for tone channel 2.
R5 W #A5
R1 but for tone channel 2, except:
R6 W #A6
b1,b0
b3,b2
b4
b5
b6
b7
R7 W #A7
b0
b1
b2
b3
R8.
b4
R12.
b6,b5
b7
R8 W #A8
b5-b0
R7.b3 = 1.
b7,b6R9 W #A9
b5-b0b7,b6R10 W #AA
b5-b0b7,b6R11 W #AB
b5-b0b7,b6R12 W #AC
b5-b0
R7.b4 = 1.
b7,b6R13 W #AD
b5-b0b7,b6R14 W #AE
b5-b0b7,b6R15 W #AF
b5-b0b7,b6R16 R/W #B0
b7-b0
A21-A14 if
A15',A14' = 00
R17 R/W #B1
b7-b0
A21-A14 if
A15',A14' = 01
R18 R/W #B2
b7-b0
A21-A14 if
A15',A14' = 10
R19 R/W #B3
b7-b0
A21-A14 if
A15',A14' = 11
R20 W #B4
b0
b1
b2
b3
b4
INT1.
b5
INT1 latch.
b6
INT2.
b7
INT2 latch.
R20 R #B4
b0
b1
b2
b3
b4
INT1 input pin.
b5
INT1 latch set.
b6
INT2 input pin.
b7
INT2 latch set.
R21 W #B5
WR0.
R21 R #B5
RD0.
R22 W #B6
WR1.
R22 R #B6
RD1.
R23 W #B7
WR2.
R23 R #B7
RD2.
R31 R #BF
b0
b1
b3,b2
M1 only, except video RAM.
VIO
#80 to #8F/
IORQ,RD,RW in video chip.
ROM
#0-#FFFF)
RD.
CART
#10000-#1FFFF)
RD,WR.
VRAM
#FC-#FF
(#3F0000-#3FFFFF) if
R31.b0 = 0.
Low for any memory access other than ROM or cartridge
(#20000-#3FFFFF) if
R31.b0 = 1.
Gated with MREQ,RD,WR in video chip.